Tailor-made synaptic dynamics based on memristive devices

The proliferation of machine learning algorithms in everyday applications such as image recognition or language translation has increased the pressure to adapt underlying computing architectures towards these algorithms. Application specific integrated circuits (ASICs) Tensor Processing Units by Google, Hanguang Alibaba Inferentia Amazon Web Services were designed specifically for and have been able outperform CPU based solutions great margins during training inference. As newer generations chips allow handling computation on more data, size neural networks dramatically increased, while challenges they are trying solve become complex. Neuromorphic tries take inspiration from biological information processing systems, aiming further improve efficiency with which can be trained inference performed. Enhancing neuromorphic memristive devices non-volatile storage elements could potentially even higher energy efficiencies. Their ability mimic synaptic plasticity dynamics brings closer role models. So far, mainly investigated emulation weights their non-volatility would enable both processes same location without data transfer. In this paper, we explore realisations different synapses build ReRAM devices, Valence Change Mechanism. These 1R synapse, NR synapse 1T1R synapse. For propose three dynamical regimes performance through criteria. discuss how addressed a reliable way. We also show experimental results measured ZrO x support our simulation claims. trade offs between connection direction device transistor. all concepts impact device-to-device cycle-to-cycle variability. Additionally, stimulation mode observed behavior is discussed.